Intel 12

The QuickAssist Accelerator ties the SoC into Intel's QuickAssist Architecture, its framework for application-specific co-processors that connect to the host computer's CPU via the standard frontside bus. This is not so very different from what AMD is proposing with its Torrenza programme, which, in part, is about establishing a framework for application accelerators that connect to the AMD CPU via the HyperTransport bus.

Intel's own take on HyperTransport, QuickPath Interconnect, is due to debut late next year as a key element of its 45nm 'Nehalem' processor architecture, and the use of the 'Quick' prefix - QuickPath, QuickAssist - may not be entirely coincidental.

Incidentally, Intel and IBM are working to deliver the same kind of approach, but using PCI Express add-in cards. That project, codename fans, is called 'Geneseo'.

Canmore, of course, doesn't need any of this, so is likely to come to market much sooner than Tolapai, especially if Intel's keeping the enterprise SoC waiting in the wings until Nehalem-based machines debut at the end of 2008.